? semiconductor components industries, llc, 2002 january, 2002 rev. 2 1 publication order number: mc100el14/d mc100el14 5vecl 1:5 clock distribution chip the mc100el14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the el14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. when low (or left open and pulled low by the input pulldown resistor) the sel pin will select the differential clock input. the common enable (en ) is synchronous so that the outputs will only be enabled/disabled when they are already in the low state. this avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. the internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. ? 50 ps output-to-output skew ? synchronous enable/disable ? multiplexed clock input ? esd protection: > 2 kv hbm, > 200 v mm ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors on clk, sclk, sel, and en . ? q output will default low with inputs open or at v ee ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul 94 code v0 @ 1/8 , oxygen index 28 to 34 ? transistor count = 303 devices http://onsemi.com device package shipping ordering information marking diagram a = assembly location wl = wafer lot yy = year ww = work week so20 dw suffix case 751d 1 20 1 20 100el14 awlyyww mc100el14dw so20 38 units/rail mc100el14dwr2 so20 1000 units/reel
mc100el14 http://onsemi.com 2 figure 1. logic diagram and pinout assignment q1 q2 q3 q4 17 18 16 15 14 13 12 4 3 5678 9 v cc 11 10 q4 q3 q2 q1 nc sclk clk clk v bb sel v ee d q 1 0 q0 19 20 2 1 v cc q0 en pin description function table * pins will default low when left open. pin function clk, clk ecl diff clock inputs sclk ecl scan clock input en ecl sync enable sel ecl clock select input q 04, q 04 ecl diff clock outputs v bb reference voltage output v cc positive supply v ee negative supply nc no connect clk* l h x x x sclk* x x l h x sel * l l h h x en * l l l l h q l h l h l (1) * all v cc pins are tied together on the die. warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. 1. on next negative transition of clk or sclk maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v necl mode input voltage v cc = 0 v cc v i v ee 6 v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) 0 lfpm 500 lfpm 20 soic 20 soic 90 60 c/w c/w q jc thermal resistance (junctiontocase) std bd 20 soic 30 to 35 c/w t sol wave solder < 2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur.
mc100el14 http://onsemi.com 3 100el series pecl dc characteristics v cc = 5.0 v; v ee = 0.0 v (note 2) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 32 40 32 40 34 42 ma v oh output high voltage (note 3) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mv v ol output low voltage (note 3) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mv v ih input high voltage (singleended) 3835 4120 3835 4120 3835 4120 mv v il input low voltage (singleended) 3190 3525 3190 3525 3190 3525 mv v bb output voltage reference 3.62 3.74 3.62 3.74 3.62 3.74 v v ihcmr common mode range (differential) (note 4) v pp < 500 mv v pp 500 mv 1.3 1.5 4.6 4.6 1.2 1.4 4.6 4.6 1.2 1.4 4.6 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.8 v / 0.5 v. 3. outputs are terminated through a 50 w resistor to v cc 2.0 v. 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peaktopeak voltage lies betwe en v pp min and 1 v. 100el series necl dc characteristics v cc = 0.0 v; v ee = 5.0 v (note 5) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 32 40 32 40 34 42 ma v oh output high voltage (note 6) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 6) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv v ih input high voltage (singleended) 1165 880 1165 880 1165 880 mv v il input low voltage (singleended) 1810 1475 1810 1475 1810 1475 mv v bb output voltage reference 1.38 1.26 1.38 1.26 1.38 1.26 v v ihcmr common mode range (differential) (note 7) v pp < 500 mv v pp 500 mv 3.7 3.5 0.4 0.4 3.8 3.6 0.4 0.4 3.8 3.6 0.4 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. input and output parameters vary 1:1 with v cc . v ee can vary +0.8 v / 0.5 v. 6. outputs are terminated through a 50 w resistor to v cc 2.0 v. 7. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peaktopeak voltage lies betwe en v pp min and 1 v.
mc100el14 http://onsemi.com 4 ac characteristics v cc = 5.0 v; v ee = 0.0 v or v cc = 0.0 v; v ee = 5.0 v (note 8) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh t phl prop clk to q (diff) delay clk to q (se) sclk to q 520 470 470 720 770 770 580 530 530 680 680 680 780 830 830 630 580 580 830 880 880 ps t skew part-to-part skew within-device skew (note 9) 200 50 200 50 200 50 ps t jitter cycletocycle jitter tbd tbd tbd ps t s setup time en 0 0 0 ps t h hold time en 0 0 0 ps v pp input swing (note 10) 150 1000 150 1000 150 1000 mv t r t f output rise/fall times q (20% 80%) 230 500 230 500 230 500 ps 8. v ee can vary +0.8 v / 0.5 v. 9. skews are specified for identical low-to-high or high-to-low transitions. 10. v pp( min) is the minimum input swing for which ac parameters guaranteed. the device has a dc gain of 40. receiver device driver device q q d d 50 w 50 w v tt typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) v tt = v cc 2.0 v
mc100el14 http://onsemi.com 5 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100el14 http://onsemi.com 6 package dimensions so20 dw suffix plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc100el14 http://onsemi.com 7 notes
mc100el14 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100el14/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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